In digital circuits, clock signals are usually used as a reference for time to define the shifting of data. In order to render every element driven by the clock signals in the circuit being capable of receiving the clock signals, a clock tree is usually generated from one of points of the clock signals or the clock source thereof so as to be used by the elements. However, there is a latency between the clock signals before and after the clock tree generation, which causes the hold time of data requiring corresponding adjustments.
FIG. 1 is a diagram illustrating the above-mentioned problem, wherein the buffer or the delay unit 11 is utilized to demonstrate a latency existing between a clock source and the clock tree generated from the clock source. It is noticed that the buffer or the delay unit 11 in FIG. 1 just represents the latency for the clock tree and is not a substantial buffer or latency unit in the design. The source end in FIG. 1 has a register 13 for receiving signals and is driven by the clock source. The data carried in the input signal is transmitted to the register 15 in the back end by the register 13, and the clock tree is generated from the clock source to drive the register 15.
In the present invention, an interface where the clock tree is generated by the clock source is termed as a clock tree conversion point. It is shown in the timing sequence diagram of FIG. 1 that the latency between the clock tree and the clock source may cause errors for element 15 when receiving the input data. The latency causes that the input signal transmitted from the clock domain of the source signal to the clock domain of the clock tree fails to be correctly received by element 15. The conventional method utilized to solve the above-mentioned problem is to use the scheme of adding the buffer or the delay unit 17 to render the input data capable of being correctly received by element 15 in timing sequence, as shown in FIG. 2, or the scheme of adjusting the rising or falling edge of the clock tree with a tunable delay unit 19 to trigger the element 15 at the correct timing sequence so as to receive the input data correctly, as shown in FIG. 3.
Though the above-mentioned concept for solving the above problem is simple, it's difficult to implement the practical circuit. Because with the increasing complexity and functionality of the input signals and back end circuits, the clock latency for balancing and compensating caused by the clock tree becomes more and more significant, which causes the above-mentioned scheme extremely complicated and impractical.
For example, as shown in FIG. 4, there are various input sources such as HDMI, Tuner, component, S, composite, and ADC input, etc. to be inputted into a display. The input sources 41˜44 in FIG. 4 have each own clock source respectively, which may range from 13.5 MHz to 300 MHz or even wider, making the balancing and compensating of the clock trees generated after multiplexer 46 with the data from various input sources extremely difficult.
Furthermore, the latency relationship between the clock and data for all the input sources must be constantly adjusted so as to balance the latency relationship between the clock and data to ensure that the first stage of the back end circuit can safely receive all kinds of data by register 47 from multiplexor 45. Since those balanced relationship must be re-adjusted once a new design, input source, floorplan, or layout is added or implemented, which is quite complicated to be implemented for the sake of complexity, time, and cost.
The applicant developed the present application to overcome the above shortcomings, and the brief illustration of the present application is as follows.